-- 32 bit version register file
-- evillase

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity memWait is
  port
    (
      nReset     : in  std_logic;
      clk        : in  std_logic;
      waitMem    : in  std_logic;
      waitMemOut : out std_logic);
end memWait;

architecture arch of memWait is

  signal r : std_logic;
  signal o : std_logic;
begin
  
  registers : process (clk, nReset, o)
  begin
    if (nReset = '0') then
      -- Reset here    
      r <= '0';
    elsif (rising_edge(clk)) then
      r <= o;
    end if;
  end process registers;

  waitMemOut <= o;

  o <= (not r) and waitMem;

end arch;
